The present inventive concept relates to memory modules, such as those commonly used in data processing apparatuses. More particularly, the inventive concept relates to memory modules capable of cutting off leakage current.
Various semiconductor devices, such as CPUs, memories, and gate arrays, implemented by integrated circuit chips are incorporated into various data processing apparatuses, such as portable personal computers, PDAs, servers, and workstations. These data processing apparatuses may be capable of operating in a sleep mode during which most of the internal circuitry is placed in a standby state in order to reduce power consumption.
Many main memories for data processing apparatuses are implemented with semiconductor memories, such as dynamic random access memories (DRAMs). Each memory cell in a DRAM is configured with an access transistor and a storage capacitor. In its operation, the DRAM may be characterized as a volatile memory device since stored data is lost in the absence of applied power. In order to maintain stored data, the DRAM must routinely perform a refresh operation.
One more specific type of SDRAM is the synchronous dynamic random access memory (SDRAM). Its operation is characterized by a three-stage pipe line that separately performs (1) input of a column address, (2) reading of data based on the address, and (3) output of the corresponding read data in synchronization with a clock signal.
Any attempt to significantly reduce the power consumption in contemporary consumer electronic products, and particularly battery powered, portable devices must address the issue of power consumption by constituent memory devices, such as the DRAM.
The incorporation of DRAMs into many data processing apparatuses is typically accomplished by means of the so-called “memory module”. A memory module is any substrate with integrated circuits mounted thereon which generally allows functional data access and common physical incorporation of memory within a host device. As routinely implemented a memory module comprises a plurality of separately packaged integrated circuit (IC) devices and related components mechanically mounted on a printed circuit board (PCB). The plurality of IC devices are electrically connected to a main board or main panel via a plurality of conductive elements called “taps”. In one configuration, a tap is formed by a connection pin to an IC device.
Servers are one type of data processing apparatus typically requiring a great deal of memory data storage capacity. Contemporary servers often incorporate one or more registered dual in-line memory modules (RDIMMs), one specific type of memory module, to provide the necessary memory capacity.
In general, a DRAM can process data during a period between reception of a column address and output of read data. In contrast, the SDRAM performs the same data processing function using the afore-mentioned three-stage pipe line, wherein each stage of the pipe line is executed synchronously with a clock signal. Thus, three clock cycles are required for initial data output after beginning operation, but thereafter data may be output for every clock cycle. As a result, it is possible to access data at relatively high speed, as compared with other types of memory.
Normally, the SDRAM processes data in synchronization with the rising edge of the clock signal. In contrast, so-called double data rate (DDR) clocking techniques have been applied to RDIMM data access operations, wherein both the rising and falling edges of a single clock signal are used to process data.
Within certain data processing apparatuses, a memory module including an x4 component may not use a data masking (DM) function due to existing error correction and/or detection (ECC) functionality. In such a case, the DM pin may be pulled down to VSS on the memory module PCB or otherwise grounded within the system. Therefore, when on die termination (ODT) is enabled, a DC current path is formed between a pull-up-side resistor of the DM pin and ground. Unfortunately, this configuration results in an unintended current flow.
Therefore, measures are required which can detect an x4 signal at the memory module component level in order to forcibly disable an ODT switch of the DM pin to cut off the resulting current path, thereby reducing power consumption otherwise occurring as a result of the DM pin configuration.